1. Technical Field
The present disclosure relates to the fabrication of modular fuses and antifuses for use in integrated circuits. Electrically operable fuses and antifuses are used for such purposes as altering circuit connections, and replacing defective circuit elements with redundant circuit elements.
2. Description of the Related Art
A fuse is a sacrificial device that is designed to protect one or more circuit elements from excess electric current. The fuse can be coupled in series with one or more the circuit elements so that an excess level of current will trip the fuse, sometimes by melting, burning or exploding, and therefore interrupt the circuit before the neighboring circuit element is damaged.
An antifuse is sacrificial device that is designed to protect one or more circuit elements from excess electric voltage. The antifuse includes two conductors and an intervening dielectric which is subject to breakdown upon application of an excess voltage between the conductors. The antifuse can be coupled in parallel with one or more the circuit elements so that an excess voltage level will break down the dielectric, causing a short circuit through the antifuse. The short circuit directs current flow away from the parallel circuit element, thereby preventing damage.
Microelectronic fuses (efuses) and antifuses are utilized within the field of integrated circuits and semiconductor processing for a number of purposes. For example, an array of efuses or antifuses can be programmably coupled to certain circuit elements to alter microelectronic circuits. Or, failed circuit elements can be replaced by redundant circuit elements, using efuses and/or antifuses.
Chemical mechanical planarization (CMP) is a polishing technique used in the semiconductor industry to planarize (make flat) the surface of a semiconductor wafer at various times during an integrated circuit fabrication process. Typically, it is desirable to planarize the wafer surface after completing deposition and patterning of a layer, before proceeding to deposit a next layer of material. If planarization is omitted, the topography of the un-planarized surface can be transferred to, or accentuated in, subsequent layers. Such topography effects are more likely to occur if materials used in subsequent layers have poor ability to fill surface recesses.
A CMP process typically entails polishing the wafer surface using a rotating pad and a slurry made from various chemicals and abrasive particulates, so that both chemical and physical removal mechanisms contribute to the planarization. Depending on the materials and the circuit features being polished, the CMP process may gouge the surface, causing CMP-induced topography and thereby degrading the surface uniformity. Such gouging of the surface is sometimes referred to as “dishing.” If local erosion is too great, the CMP process used during subsequent layers may not effectively remove material (e.g., metal) from recessed areas. Puddle defects in which residual metal is left behind in the recessed areas can cause short circuits.
When polishing metal features, dishing tends to occur disproportionally where the surface has large fields of metal as opposed to arrays of smaller metal features. Such large fields of metal are more numerous at higher metal layers which are farther away from the active transistor devices, where the metal interconnect structure is less dense and the metal lines can be made larger. It is customary to break up such large metal features by patterning arrays of small scale dummy metal features that do not participate in microelectronic circuits, but are only used to improve uniformity of the CMP process. The use of dummy structures consumes valuable real estate on an integrated circuit chip that could otherwise be used to accommodate active electronic devices. Therefore, alternatives to the use of such dummy structures are of great interest to integrated circuit manufacturers.